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Lattice Semiconductor
IP Core Generation and Evaluation
Running Functional Simulation
Simulation support for the TSMAC IP core is provided for Aldec Active-HDL (Verilog and VHDL) simulator, Mentor
Graphics ModelSim (Verilog only) simulator, and Cadence NC-Verilog (Linux only) simulator.
The functional simulation includes a configuration-specific behavioral model of the TSMAC IP core, which is instan-
tiated in an FPGA top level along with some test logic (MAC client side FIFO loop back logic, PLLs, and registers
with Read/Write Interface). This FPGA top, which is referred to as the Test Application Design, is instantiated in an
evaluation test bench that configures FPGA test logic registers and TSMAC IP core registers. The test bench also
sources Ethernet packets to the Test Application, and monitors packets from Test Application.
More information on the simulation and the Test Application Design can be found in “Application Support” on
page 48 .
The generated IP core package includes the configuration-specific behavior model (<username>_beh.v) for func-
tional simulation in the “Project Path” root directory. Lattice does not provide a test bench for evaluating this IP core
in isolation. However, a functional simulation capability is provided in which <username>_beh.v is instantiated in
the Test Application Design described in Application Support section of this document.
The simulation script supporting ModelSim evaluation simulation is provided in ?
\< project_dir >\ts_mac_eval\< username >\sim\modelsim .
The simulation script supporting Aldec evaluation simulation is provided in ?
\< project_dir >\ts_mac_eval\< username >\sim\aldec.
The Test Application Design is instantiated in a test-bench provided in ?
\< project_dir >\ts_mac_eval\testbench .
Both ModelSim and Aldec simulation is supported via test bench files provided in ?
\< project_dir >\ts_mac_eval\testbench . Models required for simulation are provided in the corresponding
\models folder.
Users may run the Aldec evaluation simulation by doing the following:
1. Open Active-HDL.
2. Under the Tools tab, select Execute Macro .
3. Browse to folder ?
\< project_dir >\ts_mac_eval\< username >\sim\aldec and execute one of the “do” scripts shown.
Users may run the ModelSim evaluation simulation by doing the following:
1. Open ModelSim.
2. Under the File tab, select Change Directory and choose the folder ?
< project_dir >\ts_mac_eval\< username >\sim\modelsim .
3. Under the Tools tab, select Execute Macro and execute the ModelSim “do” script shown.
Note: When the simulation completes, a pop-up window will appear asking “Are you sure you want to finish?”
Answer “No” to analyze the results (answering “Yes” closes ModelSim).
Synthesizing and Implementing the Core in a Top-Level Design
Synthesis support for the TSMAC IP core is provided for Mentor Graphics Precision or Synopsys Synplify. The
TSMAC IP core itself is synthesized and is provided in NGO format when the core is generated in IPexpress. Users
may synthesize the core in their own top-level design by instantiating the core in their top-level as described previ-
ously and then synthesizing the entire design with either Synplify or Precision RTL Synthesis.
IPUG51_03.0, December 2010
44
Tri-Speed Ethernet MAC User’s Guide
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相关PDF资料
TS250-130F-2 POLYSWITCH PTC RESET 0.13A SMD
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相关代理商/技术参数
TSMBG0505C 制造商:未知厂家 制造商全称:未知厂家 功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|100V V(BO) MAX|DO-215AA
TSMBG0506C 制造商:未知厂家 制造商全称:未知厂家 功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|110V V(BO) MAX|DO-214AA
TSMBG0507C 制造商:未知厂家 制造商全称:未知厂家 功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|145V V(BO) MAX|DO-214AA
TSMBG0509C 制造商:未知厂家 制造商全称:未知厂家 功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|185V V(BO) MAX|DO-215AA
TSMBG0510C 制造商:未知厂家 制造商全称:未知厂家 功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|200V V(BO) MAX|DO-214AA
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TSMBG0512C 制造商:未知厂家 制造商全称:未知厂家 功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|215V V(BO) MAX|DO-214AA
TSMBG0514C 制造商:未知厂家 制造商全称:未知厂家 功能描述:SINGLE BIDIRECTIONAL BREAKOVER DIODE|250V V(BO) MAX|DO-214AA